The proper functioning of many electronic circuits involves shifting a digital signal from one voltage level to another. For example, an internal digital logic signal may need to be converted to a higher voltage level I/O signal to allow proper communication with external circuits and/or devices. However, there are numerous circumstances in which level shifting may be required to ensure that signals are of the appropriate voltage when traveling between different circuits, or different portions of a single circuit. A circuit which performs this function is herein referred to as a “level shifter.”
A schematic of a conventional level shifter circuit is illustrated FIG. 1. Level shifter 100 includes differential inputs 110a and 110b arranged to receive differential digital logic input signals in+ and in−, respectively. The voltage levels received at in+ and in− are either in a low state at ground (GND) or a high state of VDD1. The differential inputs may be formed from transistor devices, for example, NMOS devices N1 and N2, connected between ground and differential outputs 120a and 120b, which respectively provide differential digital logic output signals out+ and out−.
Further transistor elements, for example, PMOS devices P1 and P2 may be connected between VDD2 and differential outputs and having their respective gates cross-coupled to the opposing differential output. Thus, the voltage levels of differential digital logic output signals out+ and out− are either in a low state of GND or a high state of VDD2. For a level shifter that shifts voltage levels at the input to higher voltage levels at the outputs, VDD2 is greater than VDD1. For example, VDD1 may be the relatively low voltage level of internal logic voltages and VDD2 may be the relatively high voltage level of an external circuit or device.
As discussed above, level shifters are commonly used to shift internal logic signals to higher levels appropriate for I/O signals, for example, at I/O pads designed to interface with external circuits, devices or chips. FIG. 2A illustrates an output channel of a integrated circuit adapted to provide an internal logic signal to an output pad at voltage levels required for a particular I/O interface. Output channel 200 includes an output pad OUT 210 at which an external circuit or device may connect to receive I/O signals from the integrated circuit. OUT 210 is connected to a low voltage source (VL), a mid-level voltage source (VM, which may be ground) and a high level voltage source (VH) via switches 225, 235 and 245, respectively. Ultimately, which of these voltage levels is provided to OUT 210 depends on level shifters 220, 230 and 240, as discussed in further detail below.
Level shifters 220, 230 and 240 are schematically shown, and each may be similar to the level shifter illustrated in FIG. 1. Specifically, the in+ and in− connections in each of the level shifters in FIG. 2A may correspond to the IN+ and IN− connections illustrated in FIG. 1 and are arranged to receive the internal signals from the integrated circuit. As discussed above, these signals may be internal logic signals generated by the integrated circuit and are typically at a low voltage level relative to the voltage levels required at the output pad OUT 210. Similarly, the out+ and out− connections illustrated in FIG. 2A may correspond to OUT+ and OUT− in FIG. 1, and are arranged to provide voltage levels shifted up from the voltage levels received at the inputs. The out+connection of the level shifters 220, 230 and 240 are coupled to the switches 225, 235 and 245, respectively, to control which voltage level VL, VM or VH is provided at the output pad OUT 210. For example, when level shifter 240 generates a high level voltage at out+, switch 245 is turned on and the high voltage VH is provided at OUT 210. Similarly, when level shifter 220 generates a high level voltage at out+, switch 225 is turned on and the low voltage VL is provided at OUT 210.
Thus, output channel 200 implements a voltage level shift from relatively low internal voltage levels to relatively high voltage levels appropriate for a particular I/O application. It should be appreciated that an integrated circuit may include multiple output channels. For example, FIG. 2B illustrates an integrated circuit 250 that has a multiple output pads 210′. Each output pad may be connected as illustrated in FIG. 2A to level shifters to form an N-channel I/O interface to external (e.g., off-chip) circuits or devices. In the example illustrated in FIG. 1A, only a single level shifter is provided for each voltage level in output channel 200. However, multiple level shifters may be provided in series to obtain increased voltage level shifting to accommodate I/O interfaces where significant level shifting may be required. For example, the output connections of one level shifter may be provided to the input connections of another level shifter to achieve an intermediate voltage level. This configuration may be repeated until the desired voltage level increase is achieved.